Low power in-memory implementation of ternary neural networks with resistive RAM-based synapse
Laborieux, A., Bocquet, M., Hirtzlin, T., Klein, J. O., Diez, L. H., Nowak, E., Vianello, E., Portal, J.-M., & Querlioz, D.
Laborieux, A., Bocquet, M., Hirtzlin, T., Klein, J. O., Diez, L. H., Nowak, E., Vianello, E., Portal, J.-M., & Querlioz, D.
Laborieux, A., Bocquet, M., Hirtzlin, T., Klein, J. O., Nowak, E., Vianello, E., Portal, J.-M., & Querlioz, D.
Laborieux, A., Ernoult, M., Scellier, B., Bengio, Y., Grollier, J., & Querlioz, D.
Laborieux, A., Ernoult, M., Hirtzlin, T., & Querlioz, D.
Laborieux, A., & Zenke, F.
Srinath Halvagal, M.*, Laborieux, A.*, & Zenke, F. (* equal contribution)
Laborieux, A., & Zenke, F.
Talk at UC San Francisco, Department of Testing, San Francisco, California
Tutorial at UC-Berkeley Institute for Testing Science, Berkeley CA, USA
Talk at London School of Testing, London, UK
Conference proceedings talk at Testing Institute of America 2014 Annual Conference, Los Angeles, CA